Chapter 1　Industry Overview and Definitions

Electronic Design Automation (EDA) software constitutes the foundational infrastructure of the modern semiconductor industry. If wafer foundries are the "skeleton" of semiconductor manufacturing, then EDA tools are the brain and nervous system — every logic gate, every metal interconnect, every timing constraint in a chip design must pass through EDA tools to transform from an engineer's concept into a manufacturable layout file. Without EDA software, designing chips at the three-nanometer or one-nanometer scale would be impossible.

This is not an exaggeration. A modern advanced chip — such as Apple's A17 Pro or Huawei's Kirin 9010 manufactured on TSMC's 3nm process — contains tens of billions of transistors. If its metal interconnect lines were stretched end to end they would circle the Earth multiple times, and the routing rule file alone may contain thousands of constraints. Even a team of hundreds of top-tier design engineers cannot accomplish this work with paper, pencil, or conventional electronic spreadsheets.

1.1 The Three Core Dimensions of EDA

From a functional standpoint, EDA tools divide into three core dimensions:

Functional Correctness Verification. Before tape-out, engineers must ensure that every functional state and every timing path of the chip behaves exactly as specified. EDA's simulation tools (such as RTL simulation, formal verification) perform this check. A single timing bug that reaches the fabricated silicon can make the entire chip unsalvageable.

Physical Implementability. IC design is ultimately a geometric problem — transistors and metal wires must be physically laid out on a silicon wafer in a way that satisfies manufacturing rules. EDA's place-and-route (P&R) tools solve this geometric optimization problem automatically. At the 3nm node, there can be over 3,000 design rules (DRC rules) that the layout must satisfy simultaneously.

Manufacturing Economy. EDA tools also must optimize PPA (Power, Performance, Area): chips that are too large waste silicon area and raise cost; chips that run too slow fail to meet product specifications; chips that consume too much power make thermal management infeasible. EDA tools continuously balance these three objectives throughout the design process.

1.2 The Historical Origins of EDA

Before EDA existed, IC design was pure craftsmanship. In the 1960s, engineers drew chip layouts by hand on transparent acetate sheets, then photographic reduction created the photomask. A chip containing dozens of transistors required a team of designers working for months. When transistor counts exceeded hundreds, manual design became practically impossible.

DARPA's 1979 VLSI research program funded key EDA tool development at UC Berkeley and Carnegie Mellon. The commercial EDA era began in the 1980s: Mentor Graphics was founded in 1983; Cadence Design Systems was formed in 1988 through the merger of three companies; Synopsys became independent in 1990. All three giants established their technical DNA in this golden decade.

1.3 EDA's Computational Challenges

EDA is fundamentally about transforming an engineer's high-level intent through a series of progressive mathematical transformations into geometric data (GDSII or OASIS format) that a foundry can directly manufacture. Each step in this transformation chain is an NP-Hard computational problem.

Logic synthesis requires selecting — from a Standard Cell Library — the combination of gates that optimally implements a given Boolean function, minimizing area while meeting timing and power targets. Place-and-route requires determining the physical position of millions of standard cells and routing billions of metal interconnect segments without creating shorts, satisfying DRC, and meeting timing closure. These problems are computationally intractable by brute force; EDA tools use decades of heuristic algorithms, graph-theoretic techniques, and increasingly, machine learning to find good-enough solutions in practical runtimes.

Chapter 2　Global Landscape and China's Position

2.1 The Triopoly and Its Sustainability

The global EDA market has long exhibited a heavily concentrated oligopolistic structure. Synopsys, Cadence Design Systems, and Siemens EDA (formerly Mentor Graphics) collectively hold approximately 74% market share, reaching 90%+ in certain sub-segments such as advanced node physical verification and high-end SPICE simulation.

Synopsys (SNPS) in fiscal year 2025 reported revenue of $7.054 billion (+15% YoY). Following the completion of its $35 billion Ansys acquisition on July 17, 2025, Synopsys has transformed from a pure EDA company into a "Silicon-to-Systems" full-stack tool provider, integrating structural mechanics, fluid dynamics, and electromagnetic field simulation with IC design tools.

Cadence (CDNS) in FY2025 reported revenue of $5.297 billion (+14% YoY), with core EDA growing 13% and backlog reaching a record $7.8 billion. Cadence's Cerebrus AI-driven digital implementation tool has demonstrated 20% efficiency improvements and 10x speed-ups for consumer electronics customers.

Siemens EDA (acquired from Mentor Graphics in 2017 for $14.4 billion) generates estimated annual revenue of approximately $2.5 billion. In March 2026, Siemens launched Fuse EDA AI Agent, the first multi-tool autonomous coordination EDA agent powered by NVIDIA AI, marking the formal entry of the EDA industry into the "AI Agent" era.

2.2 China's Position in the Global EDA Market

China's EDA market in 2025 is estimated at approximately RMB 18.49 billion (approximately $2.54 billion), representing about 18.1% of the global total. Three global giants collectively hold approximately 85% of the Chinese market; domestic suppliers hold approximately 10-12%.

China has approximately 3,000+ active Fabless IC design companies, which are the primary consumers of EDA tools. These companies range from tier-1 (Huawei HiSilicon, Unisoc, HiStar, Cambricon) spending RMB tens of millions annually on EDA licenses, to mid-tier companies (annual revenue of RMB 100M-1B) with EDA budgets of RMB 1-5 million, to thousands of small firms and startups relying on shared EDA platforms or university licenses.

The domestic self-sufficiency rate crossed 10% in 2024. In the flat panel display (FPD) EDA sub-segment, domestic market share exceeds 95% — a rare example of category leadership by a Chinese EDA vendor (Empyrean Technology).

Chapter 3　Tool Ecosystem (Digital / Analog / Manufacturing EDA / IP)

3.1 The Digital IC EDA Flow

The digital IC EDA flow transforms a behavioral description into manufacturable geometry through a defined sequence of tools:

RTL Design → Logic Synthesis → Floorplanning → Placement → Routing → Physical Verification (DRC/LVS) → Timing Sign-off → DFT Insertion → GDSII

Each step is a specialized software domain. Logic synthesis converts RTL to gate-level netlist using Standard Cell Libraries. Placement determines the physical location of each standard cell. Global and detailed routing connects cells with metal wires. DRC (Design Rule Check) verifies that all geometric constraints of the manufacturing process are satisfied. LVS (Layout Versus Schematic) confirms the layout matches the circuit netlist. Static Timing Analysis (STA) verifies that all timing paths meet setup and hold time constraints. DFT inserts scan chains and other test structures to enable post-manufacturing testing.

3.2 The Analog/Mixed-Signal IC EDA Flow

Analog and mixed-signal IC design follows a different flow:

Schematic Entry → SPICE Simulation → Layout → Physical Verification → Parasitic Extraction → Post-Layout Simulation

SPICE simulation solves the differential equations governing transistor behavior to predict the circuit's electrical characteristics. Unlike digital simulation (which operates at the Boolean abstraction level), SPICE simulation works at the transistor level, capturing non-linear device physics. This makes it computationally intensive — traditional SPICE handles thousands of transistors; FastSPICE extends to millions; modern DRAM arrays (billions of transistors) require hierarchical SPICE combined with machine learning surrogate models.

3.3 Manufacturing and Packaging EDA

TCAD (Technology Computer-Aided Design) simulates semiconductor device physics — dopant profiles, carrier transport, oxide growth, etching profiles — allowing foundries to develop and optimize new process nodes before committing to expensive physical experiments.

OPC (Optical Proximity Correction) compensates for the diffraction effects that cause printed patterns to deviate from their intended shapes when lithography wavelengths are much larger than feature sizes. Modern OPC uses inverse lithography technology (ILT) to compute the photomask shapes that will produce the desired silicon patterns.

DFM (Design for Manufacturability) tools verify that design patterns are robust against typical manufacturing variations, flagging structures likely to suffer yield loss.

Packaging EDA addresses the growing complexity of advanced packaging: Chiplet interconnects, 3D-IC thermal and signal integrity co-simulation, CoWoS substrate design.

3.4 IP Ecosystems and EDA Integration

Synopsys DesignWare IP generates approximately $1.7 billion in annual revenue, covering USB, PCIe, DDR, Ethernet, and hundreds of other interface and processor IP cores. Cadence's IP business exceeds $700 million annually.

The strategic value of combining EDA tools with IP is the creation of ecosystem lock-in: engineers using a vendor's EDA tools can directly instantiate that vendor's validated IP cores, creating a "tool + IP" virtuous cycle. Primarius Technologies' (concept) acquisition of Ruicheng Microelectronics (an AMS IP company with ~15% domestic market share) represents an attempt to replicate this EDA+IP platform model in China.

Chapter 4　Key Players: Fabless / Foundry / IDM / Academia

4.1 The Fabless Ecosystem Structure

China's 3,000+ Fabless IC design companies exhibit highly unequal EDA spending distribution. The top ~50 companies account for over 70% of total EDA expenditure. This concentration means that domestic EDA tools' ability to penetrate top-tier customers is decisive for market share.

Mid-tier companies (annual revenue RMB 100M-1B) represent domestic EDA's most realistic near-term target: price-sensitive enough to accept hybrid EDA arrangements, large enough to validate tools through real tape-outs, and numerous enough to provide a broad reference base.

Bottom-tier companies (startups and very small Fabless firms) are natural candidates for cloud EDA and SaaS models, which dramatically lower the upfront cost of tool access.

4.2 IDM Customer Needs

IDMs (Integrated Device Manufacturers) that own both design and manufacturing capabilities — including SMIC, HUA Hong Semiconductor, and BYD Semiconductor — have broader EDA needs than pure Fabless companies. They need not only design-side tools but manufacturing-side tools: TCAD for process R&D, OPC/ILT for lithography control, DFM for yield improvement, and in-line metrology integration.

4.3 The Research and University Ecosystem

China's top universities — Tsinghua, Peking University, Fudan, USTC, HUST — all have active EDA research groups. Government-funded programs (including a dedicated EDA sub-program under the National Key R&D Plan) provide research funding. The EDA Engineering Center (国家集成电路产业化基础平台) at Tsinghua University serves as a focal point for industry-academia collaboration.

University talent pipelines feed domestic EDA companies: approximately 800 VLSI-related PhD graduates enter the industry annually, with an increasing fraction targeting EDA algorithm roles. However, the gap between academic algorithm research and industrial-grade product engineering remains wide — a gap that requires 5-10 years of real-project experience to bridge.

Chapter 5　Application Scenarios (IC Design / RF / Packaging / PCB / EMI)

5.1 Digital IC Design: The Core EDA Market

Digital IC design for AI accelerators, mobile SoCs, server CPUs, and communications chips represents the largest and most technically demanding EDA segment. AI chip design has introduced new EDA requirements: extremely large die sizes (H100 at >800mm²), novel arithmetic data types (BF16, FP8, INT4), and 3D packaging co-design for HBM stacking.

5.2 RF and Millimeter-Wave IC Design

5G base station chips and 60GHz consumer connectivity chips require EDA tools that accurately model high-frequency electromagnetic phenomena, non-linear device behavior, and phase noise. Empyrean Technology's RFIC full-flow tools are the most comprehensive domestic solution, covering schematic to layout to EM verification for RF applications.

5.3 Advanced Packaging EDA

The transition to Chiplet architectures (AMD MI300, NVIDIA H100) and 2.5D/3D stacking (Intel FOVEROS, TSMC CoWoS, Samsung X-Cube) has created a new EDA sub-market. Package designers need tools for die-to-die signal integrity analysis, thermal co-simulation, substrate routing, and interposer design. Broadway Technology's August 2025 acquisition of LUCEDA, the global leader in silicon photonics EDA, positions it in the frontier of photonic integrated circuit (PIC) design automation.

5.4 PCB EDA

China is the world's largest PCB manufacturing country by volume (approximately 55% of global output), creating a large base of PCB design services companies that use PCB EDA tools. Domestic PCB EDA (立创EDA/EasyEDA from JLCPCB) has achieved significant penetration among small-to-medium design firms, while high-end PCB EDA (Cadence Allegro, Mentor Xpedition) dominates complex multi-layer RF and automotive board designs.

Chapter 6　National Champions: Empyrean, Primarius, Broadway, Xinyuazhang

6.1 Empyrean Technology (华大九天, 301269.SZ)

Empyrean Technology is China's leading EDA company and the world's fifth-largest EDA vendor. In 2025, revenue was RMB 1.325 billion (+8.4% YoY) with net profit of RMB 61 million (-44.3% YoY), as aggressive R&D investment (R&D expense rate 64.8%) suppressed near-term profitability.

Key 2025 milestones:

  • Launched 11 new core EDA tools and 9 key solution packages
  • Launched China's first EDA platform for memory chip mass production (supporting DRAM/Flash full-flow) in August 2025, with deployment at CXMT (长鑫存储) for DRAM yield-quality validation
  • Invested RMB 100 million in Xinyuazhang (7.78% equity) to establish digital verification collaboration
  • Terminated planned acquisition of XinHe Semiconductor due to core clause disagreements

Empyrean's product portfolio spans: analog IC full-flow, memory IC full-flow, RF IC full-flow, flat panel display IC full-flow, advanced packaging EDA.

6.2 Primarius Technologies (概伦电子, 688206.SH)

Primarius Technologies focuses on SPICE simulation and memory design. In 2024, revenue was RMB 419 million (+27.4% YoY). Its NanoSpice X and NanoSpice Pro X (launched 2025) deliver over 2x performance improvement for large-capacity memory simulation.

The proposed acquisition of Ruicheng Microelectronics (AMS IP company, ~15% domestic market share) and controlling stake in Naneng Micro represents Primarius's transformation toward an EDA+IP platform model — replicating the vertical integration logic that defines Synopsys's DesignWare IP business.

6.3 Broadway Technology (广立微, 301095.SZ)

Broadway Technology specializes in yield management EDA, DFM, and DFT tools — serving primarily wafer foundries (SMIC is a key customer) rather than Fabless companies, which reduces direct competition with the three global giants.

In 2025, revenue was RMB 735 million (+34.4% YoY) with net profit of RMB 89 million (+10.5%) — the healthiest financials among listed domestic EDA companies. The August 2025 acquisition of LUCEDA (global leader in silicon photonics/PDA) extends Broadway into a frontier application domain with global customer reach (imec, Fraunhofer, European research institutes).

6.4 Xinyuazhang (芯华章)

Xinyuazhang focuses on digital front-end verification: logic simulation (GalaxSim), formal verification (GalaxEC), and hardware-assisted verification. Its EDA 2.0 strategy (Intelligent + Open + Platform) emphasizes AI-native verification automation.

Key case: In ZTE Microelectronics deployment, Xinyuazhang's SVAEval tool improved development efficiency by 40%, compressing debug cycles from 3 days to a few hours. The ChatDV large model (developed jointly with the national EDA Engineering Center) claims 10x efficiency improvement and 10x cost reduction for digital chip verification workflows.

Chapter 7　The Five-Platform View: Data Insights from the Factory Database

7.1 Semiconductor Design Company Distribution

In the factory database platform's repository, semiconductor design companies number over 1,700 — covering the full spectrum from small Fabless design firms to large IDM enterprises. These companies are the core consumers of EDA software, and also represent the primary target customer population for upstream sales teams serving the electronics manufacturing industry.

Related manufacturing enterprises in adjacent categories include simulation software users (140+ enterprises) and verification software users (28 enterprises), reflecting the high concentration of IC verification activities among a defined set of technically sophisticated firms.

The Guowei Group (国微集团) shows 19+ associated enterprises in the database, reflecting the group's multi-faceted presence across EDA tools, IP modules, and FPGA prototype verification. Phlexing Technology (行芯科技) appears in customer enterprise records as a Signoff tool supplier to a growing roster of Fabless companies.

7.2 The PCB Manufacturing Ecosystem

EDA software demand in the PCB supply chain flows through design services companies (EMS and ODM firms) rather than PCB fabrication plants themselves. China's large electronics manufacturing base — producing approximately 60% of global consumer electronics — creates structural demand for PCB EDA tools, which in turn underpins the market for domestic PCB EDA vendors like EasyEDA.

7.3 EDA Sales Intelligence Value

For EDA tool sales teams, the factory database provides strategic value as a precision customer identification system. The ability to filter IC design services companies by revenue scale, city, and technology focus — and then access contact information — dramatically improves sales efficiency compared to traditional conference and referral channels. Fabless companies, IC packaging firms, and semiconductor materials suppliers all have comprehensive enterprise profiles in the database, enabling deep customer research and targeted sales strategy development.

Chapter 8　Pricing and Business Models (License vs. SaaS vs. IP Royalties)

8.1 The Traditional Seat License Model

EDA licensing has historically followed a "Seat License" model — annual fees per workstation per tool module. A mid-size Fabless company (300 engineers) typically pays $5-20 million annually for its EDA tool suite. The global giants offer "Full Suite" bundle discounts (30-50% below individual module pricing), creating deep ecosystem lock-in: once on a Full Suite, switching requires replacing the entire PDK adaptation infrastructure.

Contract terms are typically 3-5 years, often including "Most Favored Customer" clauses, technology upgrade commitments, and tape-out support services. Seven-year agreements exist for top-tier customers like Samsung and major Chinese Fabless companies.

8.2 Domestic EDA Pricing Strategy

Domestic EDA vendors universally employ "entry discount" strategies: pricing at 20-40% of equivalent imported tools to win non-critical design flow steps, then gradually expanding adoption as customer confidence grows. Empyrean's standard Analog IC license pricing is approximately 30-50% of Cadence Virtuoso; Primarius NanoSpice pricing is approximately 25-40% of Synopsys HSPICE.

This pricing strategy succeeds at market entry but suppresses profitability. Empyrean's ~5% net margin reflects this tension: the company operates in "revenue-subsidizes-R&D" mode, dependent on capital market funding to sustain the research intensity.

8.3 IP Royalty and Service Revenue Trends

Empyrean's technical services revenue grew 74.9% YoY in 2025 to RMB 201 million (15.2% of total revenue). This reflects EDA companies' evolution from pure license models toward "license + technical services" — deep PDK customization, design methodology consulting, tape-out support, and engineer training.

This service shift carries strategic value beyond revenue: each deep engagement embeds domestic EDA tools into customer workflows, generates product feedback, and builds switching costs that competitor offers cannot easily dislodge.

Chapter 9　Customers and Use Cases

9.1 Memory Chip Design: The Breakthrough Beachhead

CXMT (长鑫存储, China's only DRAM mass-producer) represents domestic EDA's most significant enterprise deployment to date. Empyrean's memory EDA platform was deployed at CXMT for DDR5 DRAM manufacturing validation in 2025 — moving from conceptual demonstration to production-level deployment.

Memory array design has unique EDA characteristics: high regularity of cell arrays, emphasis on parasitic extraction accuracy for capacitive cell modeling, and large-scale Monte Carlo simulation for bit-cell stability. These requirements differ from general-purpose logic IC design in ways that favor Empyrean's specialized memory EDA platform.

9.2 Flat Panel Display: The Category Domination Case

Empyrean commands over 95% penetration of domestic flat panel display driver IC design (BOE, CSOT, HKC, and others). This near-total market share in a well-defined niche demonstrates what's possible when a domestic EDA vendor achieves technical parity in a segment that the global giants under-serve (due to small market size relative to their revenue base).

FPD EDA's success provides a template: identify a niche that is technically feasible for domestic tools to address, that the global giants are less motivated to prioritize, and where Chinese customers represent a disproportionately large fraction of the global market.

9.3 SMIC Yield Management: The Foundry Partnership Model

Broadway Technology's yield management EDA deployment at SMIC (China's largest foundry) demonstrates the "foundry partnership" customer model. SMIC's yield improvements on 28nm/45nm nodes, enabled by Broadway's WAT parameter analysis and YAD yield-aware diagnostic platform, translate directly to profitability improvements that justify multi-year contract renewals.

9.4 Specialized Sector Opportunities

Aerospace and Defense. Military and space-grade IC design requires radiation hardening simulation (SEU/SEL), extreme-temperature reliability modeling, and long-lifecycle aging prediction. Chinese military electronics institutes have policy-driven preferences for domestic EDA tools, creating a protected market segment.

Financial Security Chips. Bank card, SIM, and ID card chips must comply with CC EAL5+ and other international security certifications. The data sovereignty concern around having chip design files processed by foreign tools creates demand for domestic EDA solutions among financial IC vendors like Datang Microelectronics.

Chapter 10　Investment and M&A

10.1 EDA Valuation Logic

EDA software companies command the highest valuation multiples in the software sector due to revenue predictability (>95% annual license renewal rates) and extreme customer switching costs. Synopsys pre-Ansys traded at 10-12x P/S; Cadence trades at 10-15x P/S.

A-share listed Chinese EDA companies enjoy "strategic substitution option" premiums: Empyrean traded at 25-40x P/S, Primarius at ~30x P/S, Broadway at ~20x P/S. These multiples embed market expectations for substantial domestic market share gains over 5-10 years.

10.2 The Synopsys-Ansys Combination: Industry Redefinition

The $35 billion Synopsys-Ansys merger creates a "Silicon-to-Systems" platform spanning IC EDA, structural mechanics, fluid dynamics, and electromagnetic simulation. For AI chip design — where thermal management, structural integrity, and electromagnetic interference are as critical as digital timing closure — this unified platform eliminates the manual boundary-condition handoff between IC design tools and system simulation tools.

This combination raises the competitive bar for domestic EDA: the relevant competitive universe is no longer "IC EDA" but "engineering simulation software" as a broader category. Cross-sector integration between domestic EDA companies (Empyrean, Primarius) and domestic engineering simulation software companies (e.g., Xin Zhike, CloudDev) will be a strategic necessity.

10.3 Domestic M&A Wave 2024-2025

Key M&A activities demonstrating the platform consolidation imperative:

  • Primarius: Planned acquisition of Ruicheng Microelectronics (AMS IP, ~15% domestic share) — EDA+IP integration
  • Broadway: Acquired LUCEDA (silicon photonics EDA) — geographic and technology diversification
  • Empyrean: Invested RMB 100M in Xinyuazhang (digital verification) — EDA coverage expansion
  • Empyrean: Initiated then terminated Xinhe Semiconductor acquisition — foundry EDA services integration attempt

Chapter 11　Policy, Standards, and Regulation (Dual Circulation, "Fourteen-Five", Export Control)

11.1 Export Control Timeline and Impact

2025-05-30: BIS sent letters to Synopsys, Cadence, and Siemens EDA requiring export license applications (ECCN 3D991/3E991) for EDA software exports to China. This triggered emergency compliance reviews at hundreds of Chinese IC design companies.

2025-07-02: US rescinded the EDA export restriction — reportedly in response to China's rare earth counter措施. The 33-day suspension window functioned as an industry stress test.

2026-01-15: BIS adjusted advanced semiconductor chip export license requirements to case-by-case review, extending EDA's compliance complexity into 2026.

The net effect of this policy volatility: larger Chinese Fabless companies now maintain formal EDA compliance programs; mid-tier companies accelerate "dual-track" EDA strategies combining imported tools for critical flows with domestic tools for auxiliary flows; domestic EDA vendors benefit from structural demand tailwinds driven not just by performance merit but by supply-chain risk hedging.

11.2 Big Fund III: The Capital Catalyst

Big Fund III (RMB 344 billion / ~$47 billion, operational since late 2024, covering to 2039) is the largest national semiconductor industry guidance fund ever established. EDA is explicitly prioritized, with a dedicated EDA investment target of approximately $1.2 billion aimed at building a relatively complete domestic platform by 2030.

Big Fund II had already invested in Phlexing Technology (2024, the fund's fourth EDA investment that year). Big Fund III capital deployment began in earnest in 2025 Q3.

11.3 Domestic Compliance Advantages

Domestic EDA tools are not subject to US Export Administration Regulations (EAR), enabling:

  • Free export to any country without end-user declaration requirements
  • Unrestricted use in defense, classified, and government-sensitive projects
  • Applicability in markets where US sanctions create restrictions on American commercial software

This "compliance dividend" is a concrete commercial differentiator, particularly for customers in sectors (military, financial, aerospace) with elevated data sovereignty requirements.

Chapter 12　Research Institute Outlook

12.1 AI and EDA Integration: The Trajectory to 2030

The speed of AI integration into EDA is accelerating beyond most projections:

By 2027: AI-assisted design will be standard for advanced-node SoC development — engineers will describe design intent in natural language rather than manually setting hundreds of P&R constraint parameters; AI agents will auto-generate constraints and run iterative optimization.

By 2028: AI Sign-off in specific design scenarios may become viable — ML models trained on relevant process/design styles predict timing with >95% accuracy versus traditional STA, compressing sign-off cycles from days to hours.

By 2030: End-to-end AI generation of "design intent → tape-out-ready layout" may become feasible in specific modular contexts, though full-chip automation remains a post-2035 aspiration.

The "AI-native" architecture advantage for domestic EDA: unlike the global giants whose legacy product architectures impose integration friction for AI modules, newly-built domestic EDA tools (especially those from companies less than 10 years old, like Xinyuazhang and Phlexing) can design AI inference into algorithmic cores from the start.

12.2 The Critical Mass Threshold

The research institute identifies a "Critical Mass" threshold for domestic EDA — only once reached does the industry enter a self-reinforcing positive feedback cycle:

  • Products adopted by tier-1 customers (RMB 5M+ annual EDA budget Fabless companies) for non-auxiliary core design flows
  • Companies achieving breakeven without dependence on capital market funding
  • Engineer compensation competitive with global giants' China-based teams

Estimated timelines to critical mass by segment:

  • Broadway (yield management/DFT): 2026-2027
  • Primarius (memory SPICE simulation): 2027-2028
  • Empyrean (analog IC full-flow): 2028-2030
  • Advanced-node digital IC full-flow: post-2030

12.3 The Research Institute's Overall Judgment

Four key judgments:

First, strategic importance is not in doubt, but timelines must not be underestimated. Domestic EDA is irreplaceable for China's semiconductor self-sufficiency agenda; policy support certainty is high. But advanced-node core tool self-sufficiency requires 10-15 years of engineering accumulation — there are no shortcuts.

Second, differentiation strategy is the only viable path in the current phase. Frontal competition against the global giants' full-product range is infeasible with current resources. Building local leadership in specialized nodes (memory, FPD), specialized functions (yield management, DFT), and emerging domains (photonics EDA, AI-EDA) is the only realistic path to building market credibility and capital accumulation.

Third, AI is a dual-valence variable. Global giants embedding AI into mature tool chains will further extend product leads; but AI also enables rapid capability leaps in specific sub-problems, providing domestic EDA a window for leapfrog progress in specialized scenarios. Capturing this window requires sufficient real design data for AI model training — which requires first establishing tool deployments at key customers.

Fourth, ecosystem integration is the long-term competitive determinant. Single-point tools, however excellent, deliver limited value if they cannot integrate into customers' broader design flows. Advancing interoperability standards among domestic EDA tools — building a "domestic EDA ecosystem" rather than a collection of isolated tools — is a critical strategic mission for 2026-2030.

Chapter 13　Risks: Supply Chain IP / Talent Loss / Customer Dependence / Price Wars

13.1 Supply Chain IP Lock-In

The deepest moat protecting the global giants is not algorithm superiority alone, but the accumulated PDK and runset ecosystem. TSMC's 3nm DRC runsets are written specifically for Calibre format; Silicon Design Kits for each node take years to develop and validate. Switching EDA tools requires replacing the entire PDK adaptation infrastructure — a 1-2 year engineering project at minimum.

For domestic EDA tools, establishing PDK compatibility at leading foundries (currently limited to SMIC for most domestic tools, with zero coverage at TSMC, Samsung, GlobalFoundries) is a prerequisite for serving the large fraction of Chinese Fabless companies that tape out at international foundries.

13.2 Talent Scarcity

The estimated nationwide inventory of engineers with core EDA algorithm development capability (compiler-level, not user-level) is under 5,000, with annual additions under 800. The required skills profile — computer science algorithms + IC design domain knowledge + applied mathematics — is exceptionally rare.

The generational risk is acute: core algorithm teams at domestic EDA companies skew toward 40-55 year olds; the next generation (under 35) is still developing the depth of experience needed for independent algorithm innovation. Knowledge transfer systems, systematic documentation, and long-term university partnerships are organizational imperatives, not optional programs.

13.3 Customer Dependence and Adoption Friction

The "dual-track" adoption strategy — keeping imported EDA for critical flows while trialing domestic tools on auxiliary flows — is rational from the customer perspective but creates a structural challenge for domestic EDA: tools deployed only on non-critical flows generate limited revenue, limited reference cases, and limited opportunities to accumulate the real-design data needed for AI model training.

Breaking out of the "auxiliary-only" trap requires demonstrating production-quality results on at least one critical flow step for at least one tier-1 customer. The CXMT memory EDA deployment and the SMIC yield management deployment are the current examples of this barrier being crossed.

13.4 Price War Dynamics

Domestic EDA's 20-40% pricing vs. imported tools is a market entry tactic, not a sustainable competitive position. As domestic tools expand adoption, two pricing dynamics will emerge:

Upward pressure: As tool capability improves, domestic vendors will seek to narrow the price discount — necessary to generate sufficient margin to fund R&D at the required intensity.

Downward pressure: Global giants facing domestic competition may implement defensive China-market pricing (narrowing the gap from 3-5x to 1.5-2x), reducing domestic tools' price-based competitive advantage.

Surviving this transition requires domestic EDA vendors to build non-price differentiation (service depth, ecosystem integration, compliance advantages) before margin pressure materializes.

Data Sources

All data, analysis, and conclusions in this report draw primarily from public sources compiled as of June 19, 2026.

Factory Database — Covering China's 480 million active factories: Semiconductor Design, EDA Software, Simulation Software, Verification Software

Company Financial Reports: Empyrean Technology 2025 Annual Report (301269.SZ); Primarius Technologies 2024 Annual Report (688206.SH); Broadway Technology 2025 Annual Report (301095.SZ)

Global Data Sources: Synopsys FY2025 Earnings Release; Cadence Design Systems FY2025 Earnings Release; BIS Federal Register Notices (May 30, 2025; July 2, 2025; January 15, 2026); SEMI China EDA Market Report 2025

Academic Sources: IEEE Design Automation Conference (DAC) 2025 Proceedings; IEEE/ACM ICCAD 2025 Proceedings; CSIA EDA Working Group Interoperability Draft Specification 2025

News and Analysis: Company press releases (Empyrean memory EDA platform launch, August 2025; Broadway LUCEDA acquisition, August 2025; Siemens Fuse EDA AI Agent launch, March 2026; Synopsys-Ansys merger completion, July 17, 2025)

This report is prepared by the Industrial Research Institute. All views expressed are research-based assessments as of the publication date and do not constitute investment advice.