June 2026, at Changxin Memory Technologies (CXMT) 300mm wafer fab in Hefei Economic Development Zone, a polished silicon wafer is sliding across the worktable of an immersion DUV scanner that has been through multiple in-house upgrades. After several hundred process steps, the wafer is diced into D1z-node DDR5 dies — the mainstream node for China's domestic DRAM in 2025-2026. By year-end, CXMT's monthly wafer-equivalent capacity has climbed to 300,000 wafers, with DDR5 yield stabilized at 80% and targeted to break 90% within the year.
At the same time, inside Yangtze Memory Technologies Corporation (YMTC) fab in Wuhan Optics Valley, an "all-domestic" production line is running its pilot phase. 300mm wafers go through the X4-to-X5 generation 3D NAND stacking, reaching the equivalent of 294 layers. The 15,000 wafers/month target for 2025-2026 corresponds to roughly 15% of the global NAND Flash supply landscape.
The 2025 global memory market is a classic story of "ice and fire". On one side, DRAM prices have risen for four straight quarters under AI compute pull, HBM supply remains tight, and Samsung Electronics, SK Hynix, and Micron Technology have all delivered record results. On the other, consumer NAND has been forced into production cuts due to weakening demand from smartphones, PCs, and enterprise IT. SK Hynix has, for the first time, surpassed Samsung Electronics in full-year operating profit in 2025 — a historic shift in a market that Samsung has dominated since the 1980s.
Looking back at China, the story is even more dramatic. After being placed on the entity list, YMTC has not, as outsiders predicted, frozen capacity — instead, it has pushed monthly output from 90,000 wafers up to nearly 130,000 by 2025-end via domestic equipment substitution. CXMT, skipping the D1y node and going straight to D1z DDR5 mass production, showcased its full DDR5 and LPDDR5X product line at IC China Q4 2025, hitting 8,000 Mbps peak speeds. The four module-house listed companies — Longsys (江波龙), Biwin (佰维), DMOST (德明利), and Shannon Semiconductor (香农芯创) — together approach 80 billion yuan in 2025 revenue, repositioning themselves from "SMT assemblers" to mid-stream platforms managing pricing, branding, and inventory cycles.
This is China's memory chip industry in 2025-2026. From "broad absence" to a four-track parallel landscape of "DRAM via CXMT, NAND via YMTC, HBM via CXMT + Tongfu, modules via the four module houses". For the first time, it has a clear path to "board" the AI HBM wave, and for the first time it has systematically completed localization of critical equipment under sustained geopolitical pressure. This report uses fourteen chapters to answer one root question: where does China's memory chip self-reliance now stand on DRAM, NAND, HBM in 2025-2026 — and what gets through, what gets stuck, between 2026 and 2030?
Chapter 1 Global memory industry overview: the 2025 pie and its polarization
The 2025 global memory market is a story of "ice and fire, HBM vs consumer NAND polarization".
Total size: about USD 180 billion in 2025, +25% YoY. DRAM about USD 123 billion (+40%), NAND Flash about USD 58 billion (-10%). HBM, the high-end DRAM segment, reached about USD 35 billion (doubled YoY). Micron projects HBM TAM to hit USD 100 billion by 2028, a five-year CAGR near 40% — a structural divergence unseen in the past thirty years.
DRAM: Samsung Electronics, SK Hynix, and Micron Technology together hold over 95% global share. Per Counterpoint Research and TrendForce quarterly data, in Q1 2025 SK Hynix took the No. 1 spot for the first time with 36% revenue share vs Samsung's 34%. By Q1 2026, Samsung clawed back to 38%, SK Hynix at 29%, Micron stable around 24%. The tug-of-war reflects "who ramps HBM faster, who captures AI compute orders first".
HBM: in Q2 2025, SK Hynix held 62% of shipments and 57% of revenue. In Q3, Samsung's HBM revenue share jumped from 15% to 22%, overtaking Micron at 21%. The 2026 HBM4 forecast: SK Hynix 54%, Samsung 28%, Micron 18%. SK Hynix has already secured ~70% of NVIDIA's HBM4 orders.
NAND: Samsung, SK Hynix (with Solidigm), Kioxia + SanDisk, Micron, and YMTC together account for ~98% of global share. In 2025, all major NAND vendors restarted production cuts of 15-20% to stabilize prices.
Prices: DRAM exited the trough in H2 2024 and rose throughout 2025; DDR5 8Gb spot price climbed from below USD 3 to nearly USD 5 by year-end. HBM3E prices stayed high, with vendors signaling another ~20% hike for 2026 driven by NVIDIA H200, AMD MI300 ASICs, and hyperscaler in-house AI chips. NAND lagged: prices rose modestly in 2025, with H2 2026 expected to enter a new uptrend driven by AI server QLC/PLC large-capacity SSDs.
End-market structure: about 30% smartphones, 20% PC/laptop, 25% data center/server (including HBM), 10% automotive/industrial, 15% other consumer electronics. The data center/server segment grew fastest — from under 20% in 2023 to over 25% in 2025, projected to break 40% by 2030, driven by large model training and inference.
Geographic distribution of memory wafer capacity 2025: Korea (Samsung, SK Hynix) ~50%; Japan (Kioxia Yokkaichi and Kitakami) ~15%; US (Micron Boise, Idaho, Massachusetts) ~15%; China mainland (YMTC Wuhan, CXMT Hefei) ~15%; Taiwan (Nanya, Winbond) under 10%. China's share is the fastest-growing of any region, projected to break 20% by 2030.
Chapter 2 DRAM technology nodes: from 10-nm class to 1γ, and the HBM process logic
DRAM node evolution is one of the most representative "continuous shrink" stories in semiconductor history, yet its trajectory differs sharply from logic.
Logic shrinks roughly 0.7x per two-year cycle following Moore's law. DRAM nodes refer to the storage cell's minimum half-pitch, not the transistor gate length. Below ~20 nm, shrink slowed because the 1T1C storage cell requires the capacitor to hold sufficient charge for reliable read/write — too small an area, and the capacitor can no longer retain charge.
To break this bottleneck, the industry introduced the 1x, 1y, 1z series of nodes with incremental shrink plus process innovation. 1x (18-19 nm) mass-produced 2015-2016; 1y (17 nm) 2017-2018; 1z (16 nm) 2019-2020. After 1z came 1α (14 nm), 1β (12 nm), 1γ (10 nm), corresponding to 2021, 2023, 2025 mainstream production.
The key technical challenge at 1α/1β/1γ shifted from line-width shrink to "maintaining capacitor capacity in a smaller footprint". Innovations include high-K dielectrics, vertical capacitors, double/multi-patterning, and EUV lithography. SK Hynix introduced EUV first on 1α in 2021; Samsung followed on 1α in 2022; Micron held back until 1γ in 2024. EUV cut the exposure count from over 30 layers to about 20, slashing process steps by ~15% and raising yields and throughput.
CXMT lags global leaders by four to six years on DRAM. Established 2017, it mass-produced 19 nm (1x) LPDDR4X in 2019, 17 nm DDR4 in 2021, D1z DDR5 in 2023, then drove D1z DDR5 to monthly shipments in the millions by 2025. Notably, CXMT skipped 17 nm as the commercial DDR5 node and went straight to D1z (16 nm), reducing one iteration's cost and risk.
CXMT's next node D1α (~14 nm) targets R&D completion in H2 2026 and mass production in 2027. The critical challenge: replacing EUV with multi-patterning for key layer definition without EUV. The benefit is no EUV dependence; the cost is more process steps and yield pressure. Industry consensus: "difficult but not impossible" — the swing variable is whether CXMT can drive multi-patterning maturity close to EUV's.
HBM process logic differs from regular DRAM. HBM dies use DRAM nodes typically one to two generations behind the latest DDR node, because HBM value lies in bandwidth — vertically stacking DRAM dies and connecting them via TSV silicon vias delivers bandwidth several times higher per unit time than DDR dies. Each HBM generation evolves via stack count and per-stack bandwidth: HBM2 8-layer 256 GB/s; HBM2E 8-layer 410 GB/s; HBM3 12-layer 819 GB/s; HBM3E 12-layer 1225 GB/s; HBM4 16-layer near 2000 GB/s.
HBM4 is the ticket to the next AI compute round. From Blackwell's successor onward, NVIDIA switches fully to HBM4 and requires 16-Hi support. SK Hynix completed HBM4 mass-production readiness in early 2026 and secured ~70% of NVIDIA's orders. Samsung delivered paid final HBM4 samples in early 2026. Micron prepares HBM4 mass production for Q2 2026.
China's HBM path remains at HBM2/early HBM3. CXMT HBM2 samples are with Tongfu Microelectronics for packaging validation; HBM3 targets 2026 mass production, HBM3E by 2027. This means China's HBM will trail global leaders by two generations in 2026-2027 — by the time SK Hynix mass-produces HBM4, CXMT enters HBM3; by HBM5, CXMT reaches HBM4. Closing this gap between 2028 and 2030 is the critical battle for domestic HBM "boarding" AI compute.
Chapter 3 NAND Flash process evolution: from 2D planar to 300-layer stacking
NAND Flash process evolution is another unique curve over the past fifteen years.
Planar 2D NAND was the only form before 2013. Cells used floating-gate or charge-trap transistors, with continuous shrink from 130 nm down to 15 nm. Below 15 nm, charge interference and reliability hit physical limits.
In 2013 Samsung mass-produced 24-layer V-NAND, switching from planar to vertical 3D stacking. The trade — more complex process steps for higher density — has driven stacks from 24 → 32 → 48 → 64 → 92 → 128 → 176 → 232 → 300 layers, multiplying bit density per wafer area by over twenty-fold. As of 2025, Samsung has released 286-layer V9 and plans 430-layer V10 for 2026; SK Hynix mass-produces 321-layer V8; Kioxia/SanDisk has 218-layer BiCS gen 8 and plans 332-layer BiCS10 for 2026-2027; Micron mass-produces 232-layer G8 with plans for 300+ layer G9.
3D NAND's core engineering challenges aren't layer count itself but stacking complexity: uniform word-line metal deposition per layer; channel-hole etching from top through bottom with vertical sidewalls; uniform charge-trap layer deposition across all layers; stable inter-layer dielectrics and interconnects through dozens to hundreds of layers. Every added layer means more process steps, longer cycle time, higher equipment cost, and lower yield. The "layer race" rewards whoever can hold commercial yield and cost at higher counts.
YMTC's 3D NAND path: 32L Xtacking gen 1 in 2018; 64L gen 2 in 2020; 128L gen 3 in 2021; 192L gen 4 in 2022; 232L X4-9070 in 2023; X5 (300-layer equivalent) for 2025-2026 ramp. Roughly one full generation every two years — the world's fastest cadence.
Xtacking, YMTC's architecture, splits the NAND array and peripheral logic across two wafers, then bonds them via billions of bond pads. The benefit: each half can use its optimal node — peripheral logic at 28/22/14 nm advanced logic nodes, NAND array on storage-optimized processes. In February 2026 Samsung publicly announced it would use parts of YMTC's Xtacking patent portfolio on its next-generation NAND — the first time a Chinese NAND vendor has reverse-licensed a global leader, signaling international recognition for Xtacking.
The 2025 global 3D NAND landscape: Samsung 286L V9, Kioxia/SanDisk 218L BiCS gen 8, SK Hynix 321L V8, Micron 232L G8, YMTC 232L X4-9070 (294L equivalent). The China-global gap narrowed from two-three generations to within one.
Multi-bit cell evolution: SLC, MLC, TLC, QLC, PLC. SLC has effectively exited mainstream (kept for industrial, automotive, high-endurance); MLC retired; TLC mainstream for consumer and enterprise SSDs; QLC emerging for low-cost large-capacity (data-center cold storage); PLC next-gen for ultra-large hyperscale archive. YMTC X4-9070 is 232L TLC, X4-6080 is 232L QLC; X5 covers TLC and QLC; PLC planned for X6.
Interface speeds rose from 100 MT/s to 200/400/800/1600/2400/3600/4800 MT/s. Each speed step requires SSD controller, PCIe protocol, and signal integrity to upgrade. YMTC X4 is 3600 MT/s; X5 targets 4800 MT/s, aligned with Samsung/Kioxia/Micron same-generation products.
YMTC capacity climbed fastest globally: 10k wafers/month in 2018, 30k in 2020, 70k in 2022, 100k in 2023, ~130k by mid-2025, target 150k for 2026, with 300k+ by 2030 — corresponding to over 20% of the global supply landscape.
Chapter 4 Major vendors: YMTC, CXMT, and the overseas giants
YMTC was founded in 2016 by Tsinghua Unigroup, Wuhan Xinxin (XMC), the National IC Industry Fund, and Wuhan municipal government, with registered capital of RMB 20.7 billion. By end-2025 monthly capacity ~130k wafers, ~8% of global NAND. Core products include X4-9070 232L TLC, X4-6080 232L QLC, and the X5 series targeting 2026 production. Product lines span consumer SSDs, enterprise SSDs, and embedded storage. Enterprise SSDs grew fastest — single-quarter revenue share rose from under 15% in 2023 to nearly 35% in 2025. Estimated 2025 total revenue near RMB 70 billion, +40%+ YoY — the first Chinese memory original-IDM to break RMB 50 billion annual revenue.
CXMT was founded in 2016 by Hefei municipal government, Hefei Industrial Investment, GigaDevice, and Innotron Memory, with registered capital around RMB 7.5 billion. By end-2025 capacity ~300k wafers/month, ~6% of global DRAM. Core products include D1z DDR5, LPDDR5X, DDR4, LPDDR4, plus HBM2 samples developed with Tongfu Microelectronics. CXMT showcased the full DDR5 and LPDDR5X line at IC China Q4 2025, hitting 8000 Mbps DDR5 and 24Gb single-die capacity. Estimated 2025 revenue near RMB 60 billion, +50% YoY; valuation already at RMB 140 billion; IPO tutoring started July 2025, on track to become "China's first memory chip stock".
Samsung Electronics: memory revenue ~USD 70 billion in 2025, +20% YoY. HBM lagged SK Hynix in 2025 (Q2 share only 15%, Q3 caught up to 22%), the biggest strategic shortfall of 2024-2025. Counter-strategy is heavy HBM4 investment with paid final samples delivered to NVIDIA in early 2026. On NAND, Samsung released 286L V9 in 2025 and plans 430L V10 for 2026 — still the global NAND process leader.
SK Hynix: the 2025 biggest winner. Full-year operating profit overtook Samsung Electronics for the first time. Holds 62% of HBM shipments and 57% of revenue by Q2 2025, and ~70% of NVIDIA HBM4 orders. NAND: Solidigm at 192L, HQ at 321L V8, with 400L+ V9 in planning. 2025 revenue ~USD 55 billion, +50% YoY.
Micron Technology: 2025 also strong, HBM share rose to 21% (briefly No. 2 in Q3 before Samsung overtook). 232L NAND in production, HBM4 16-Hi in development. 2025 revenue ~USD 35 billion, +40% YoY. CEO publicly forecasts HBM TAM at USD 100 billion by 2028, near 40% CAGR.
Kioxia: Japan's NAND leader, spun off from Toshiba memory, completed IPO 2024. 2025 revenue ~USD 13 billion, +10% YoY. Operates Yokkaichi and Kitakami fabs with SanDisk. Core 2026-2027 plan: BiCS10 (332L) mass production and ramp at new Kitakami K2 (opened September 2025). SanDisk spun off from Western Digital in 2025 for independent listing, focused on NAND and storage modules.
Cross-vendor comparison reveals five key gaps — business model (full-IDM vs die-only); R&D spend (Samsung ~USD 8B, SK ~5B, Micron ~3B, Kioxia ~2B, YMTC ~USD 1.4B, CXMT ~1.3B); process node (DRAM gap one-to-two generations, NAND within one generation); HBM cadence (SK already at HBM4, CXMT just entering HBM3 — two generations behind); and market position (SK leads DRAM/HBM, Samsung leads NAND, YMTC and CXMT are China's only scale players pushing toward global No. 4/5).
Chapter 5 AI compute drives HBM: supercycle and the domestic path
2023-2026 has seen the most dramatic structural shift in memory in three decades — HBM moved from niche product to the most profitable, fastest-growing, most contested core segment.
It began with explosive demand for memory in large model training. Post-ChatGPT, global model training compute demand grew tens of times in three years. One NVIDIA H100 GPU needs 80 GB HBM3; next-gen H200 ups to 141 GB HBM3E; B100/B200 to 192 GB HBM3E; R100/Rubin to 288 GB HBM4. Per-GPU HBM doubles each generation; shipment volumes also double yearly; total HBM demand has multiplied more than tenfold in three years.
Supply lagged badly. HBM is not ordinary DRAM — it's DRAM + TSV + TC bonding + buffer logic die + SiP system-in-package, layered tech. Only three vendors could make HBM: SK Hynix (earliest mover, leader on HBM2/2E/3/3E); Samsung (entered seriously at HBM3); Micron (first HBM3 mass production in 2023, latest entrant).
This explains why SK Hynix became 2025's biggest memory winner: 62% HBM shipment share, 57% revenue share through Q2 2025, the de facto sole supplier for NVIDIA H100/H200/B100, ~70% of HBM4 orders. Its 2025 operating profit overtook Samsung Electronics — the first major rewrite of memory industry rankings since the 1980s.
Samsung's comeback is equally notable. Q3 2025 HBM revenue share jumped from sub-20% to 22%, overtaking Micron to No. 2. HBM4 paid final sample delivered. Samsung's advantage is full IDM integration — internal logic fab for the buffer logic die, in-house advanced packaging capacity for TC bonding, internal DRAM process base. Neither SK Hynix nor Micron has all three.
Micron is the "steady No. 3". HBM3 in 2023, HBM3E in 2024, HBM4 in 2026 — one to two quarters behind SK, one to two quarters ahead of Samsung. Micron's edge: yield and stability, including industry-leading HBM3E 12-layer yield, making it NVIDIA's "backup supplier" for H200/B200.
China's HBM journey begins in 2022. CXMT + Tongfu started HBM2 sample R&D, completed first samples in 2023, process validation in 2024, full HBM2 packaging solution in 2025. CXMT also started HBM3 R&D — plan: H1 2026 HBM3 samples, H2 2026 to 2027 HBM3E.
Understanding domestic HBM progress requires parsing five environments: DRAM die (CXMT D1z gives HBM2E/early HBM3 capability); TSV silicon vias (CXMT + CSMI domestic equipment partner); TC bonding (Tongfu, JCET, Hua Tian advancing equipment localization); buffer logic die (CXMT + domestic fabless + foundries); SiP packaging (Tongfu lead).
The three bottlenecks for 2026 domestic HBM ramp: domestic equipment maturity (high-aspect-ratio TSV etchers, TC bonders, wafer thinners all on the late-2024 export-control list, with domestic vendors — CSMI, NAURA, KingSemi, HwaTsing — accelerating); yield ramp (TSV density, micron-level TC alignment, 12-layer stack yield from sub-80% to over 70% overall); GPU co-validation (HBM must be validated with domestic GPUs/ASICs from Huawei Ascend, Cambricon, Enflame, Biren, Moore Threads).
By 2026 global HBM demand is roughly 15-20 billion GB (about 1.2 billion HBM3E 12-Hi dies). NVIDIA takes 60-70%, AMD ~10%, hyperscaler ASICs 20-30%. China GPU/ASIC share was negligible before HBM3 production but will grow rapidly from 2026 onward as domestic models advance. CXMT's HBM3 production in 2026 directly serves this domestic demand growth.
Chapter 6 Domestic memory module ecosystem: Longsys, Biwin, DMOST, Shannon Semiconductor
The middle layer — memory modules — is the thickest layer China has grown in the past decade. Original IDMs make dies; module houses board them onto SSDs, DIMMs, cards, USB drives, and sell to OEM brands or end users. The layer looks "low tech" but bears pricing-cycle hedging, customer relationships, brand and channel operation, and inventory management.
The four module house listed companies — Longsys, Biwin, DMOST, Shannon Semiconductor — form China's "four dragons" of the module ecosystem.
Longsys, founded 2000 in Shenzhen, is China's largest independent module company. Coverage: embedded storage (eMMC, UFS), SSDs (consumer, enterprise, industrial), DIMMs (DDR4, DDR5), removable storage (cards, USB). Core customers: Xiaomi, OPPO, vivo, Huawei, Transsion, Alibaba Cloud, Tencent Cloud, ByteDance. 2025 revenue is projected at RMB 22.5-23 billion, +30%; net profit RMB 1.8-2.2 billion, more than doubled. Strategy: "die procurement + in-house controllers + brand operation" — sourcing dies from YMTC/CXMT and global vendors, investing in domestic controller houses, selling under FORESEE and Lexar (acquired in 2022).
Biwin, founded 2010 in Shenzhen, IPO'd on STAR Market in 2023. Focus: embedded storage (eMMC, UFS, SPI Nand) and SSDs. 2025 revenue RMB 11.302 billion, +68.82%; net profit RMB 853 million, +429.07% — the biggest YoY jump among Chinese memory module listcos. The cause: aggressive 2024 inventory buildup at price lows, then huge inventory revaluation gains as DRAM and NAND rose through 2025. Biwin year-end inventory reached RMB 7.868 billion, up over RMB 4 billion YoY; the company chose to maintain high inventory, betting on 2026 continued price rises.
DMOST, founded 2009 in Shenzhen, IPO'd on ChiNext 2023. Focus: SSD controllers + storage modules. 2025 revenue projected RMB 10.3-11.3 billion, +115-137%, the second-largest YoY jump. Year-end inventory RMB 7.058 billion, up over RMB 2.5 billion. Distinctive "controller + module deep integration" — DMOST is one of few Chinese players vertically integrating both controller and module.
Shannon Semiconductor entered the storage module and distribution business in 2022 via consolidation of Lianhe Chuangtai. Business: "OEM agency + module manufacturing + distribution". A core mainland distributor for SK Hynix, Kioxia, YMTC. 2025 revenue RMB 35.251 billion, +45.24%; net profit RMB 544 million, +106.06%. Largest among the four; lowest gross margin (distribution model); fastest revenue elasticity in upcycles.
The four combined approach RMB 80 billion 2025 revenue, exceeding the total of any single Chinese fabless company. Modules in China are no longer "low-tech SMT shops" but a mid-stream strategic node connecting IDMs with OEM brands.
Chapter 7 Platform perspective: factory indexing across the memory chain
A qualified memory report must answer concrete user questions — "find packaging houses that can package 232L NAND dies"; "find OEMs running high-end DDR5 DIMM lines"; "find SSD controller fabless companies"; "find HBM interposer packaging houses". These "by-process, by-scene, by-geography" queries require not a report but a factory index that can be filtered along multiple dimensions.
「Tianxia Gongchang」(天下工厂, literally "Factories Under Heaven") is a B2B platform focused on factory-feature matching — a database of 4.8 million active factories. Distinct from generic business-info databases (which key on registered capital, legal representative, shareholders), this platform's core dimensions are "is the company really running this process? Does it have this line? Which city? What scale? Upstream or downstream?". China's memory chip supply chain — from wafer IDMs to packaging houses, controller fabless to module houses, PCB to DIMM SMT lines, mold houses to package printing, power management chip suppliers to capacitor/inductor makers — can all be located through this dimensional index.
A few concrete sales scenarios:
Packaging equipment sales rep: representing an HBM interposer packaging tool maker. Searching the factory database by "semiconductor packaging" + "advanced packaging" + "system-in-package" returns 20-30 packaging houses with relevant capability — Tongfu, JCET, Hua Tian, China Wafer Level, Yongsi Electronics — that can be further narrowed by region.
SSD controller chip distributor: representing a PCIe 5.0 SSD controller. Searching by "memory module" + "SSD" + "PCIe" returns module houses including Longsys, Biwin, DMOST, Unionman, Goke, Yinxin. Adding signals like registered capital, headcount, SSD-engineer hiring activity surfaces customers with highest procurement intent.
Electronic specialty gas sales rep: representing high-purity etching gases (e.g., C4F8, SF6) for 3D NAND high-aspect-ratio etch. Searching by "wafer manufacturing" + "3D NAND" + "advanced etching" returns YMTC, CXMT, Hua Hong, Shanghai Active Energy, SMIC Shaoxing. Combining with "recent capex announcements" and "listco equipment-order disclosures" predicts which fab is most likely to add gas procurement in 2026.
PCB sales rep: representing high-density HDI PCB. Searching by "memory module" + "DDR5" + "DIMM" returns Longsys, Biwin, Ramaxel, Apacer, Geil, Team. Adding "DDR5 product line" and "high-speed memory" narrows to HDI customers.
Mapped to the full memory chain, factory indexing reveals: concentration is high (only 2 IDMs, ~10 packaging core houses, <20 controller fabless, 5-8 module houses above RMB 10 billion); second-tier supply is broad (hundreds to thousands of suppliers per IDM/packaging/module house); "factory identification" is hard (many companies bear "semiconductor" in name but aren't really producing); geographic clusters are clear (IDMs in Wuhan/Hefei, advanced packaging in Yangtze River Delta, modules in Shenzhen/Hefei/Dongguan); capacity ramp cadence is defined (2024-2026 IDM ramp, 2026-2028 modules + packaging + controller, 2028-2030 international expansion).
Chapter 8 Export controls and self-reliance breakthrough
China's memory industry has been at the front of US-China tech tension for the past five years. Five waves of US export control upgrades from 2018-2026:
2018: Fujian Jinhua placed on the entity list for alleged Micron trade-secret theft, effectively halted.
2020: Huawei HiSilicon's high-end chip designs placed under export controls, indirectly affecting Huawei's high-end HBM/server DRAM procurement.
October 2022: YMTC placed on the entity list; exports of <14 nm logic, ≥128L 3D NAND, ≤18 nm DRAM-related tools to China heavily restricted.
2023: Joint US/Japan/Netherlands controls extending equipment restrictions (EUV, advanced DUV, wafer transport, TC bonding) from US firms to Canon, Nikon, Tokyo Electron, ASML.
Late 2024: HBM3/3E and supporting packaging/test equipment cut off entirely from legal commercial channels to China; US semiconductor equipment makers' field-service engineers required to leave CXMT (December 2024).
Stacked, the logic is clear: lock China out of advanced node + advanced equipment + advanced protocols. Mature nodes (≥28 nm), 2D NAND, low-end niche DRAM are not blocked; <18 nm advanced DRAM, ≥128L 3D NAND, ≥HBM2 high-bandwidth memory are.
China's response far exceeded US expectations. YMTC, instead of stalling like Fujian Jinhua, lifted monthly capacity from 90k to 130k wafers through domestic equipment substitution and process re-engineering. By H2 2025, YMTC announced its first "all-domestic" production line is in pilot — all front-end, mid-process, and back-end equipment from domestic vendors. Initial capacity is small (1-2k wafers/month) but it has "independent operation" capability — no further US controls can disrupt this line's ramp.
CXMT, with no EUV, drove D1z (16 nm) DDR5 to production and kicked off D1α (14 nm) R&D. Core strategy: "multi-patterning to replace EUV" — using DUV scanners for quadruple/sextuple patterning to achieve EUV-equivalent resolution. The cost: more steps, yield pressure; the benefit: no dependence on US/Japan/Netherlands EUV. SK Hynix briefly used this path before introducing EUV on 1α. If CXMT can lift multi-patterning maturity close to EUV by 2026-2027, the D1α node can be commercialized without EUV.
HBM domestic breakthrough is more challenging. Critical equipment: high-aspect-ratio TSV etchers, TC bonders, wafer thinners, high-density BGA packaging, wafer-level test — all on the late-2024 export control list. Domestic vendors — CSMI (TSV etch), NAURA (deposition), KingSemi (coating), HwaTsing (CMP), Silicon Microelectronics (packaging/test) — are accelerating. CSMI's TSV etcher has been validated on CXMT and YMTC HBM lines; estimated 2026 shipments ~2000 units, RMB 400-700 million revenue; 2027 ~5000 units. This is the core delta for domestic HBM equipment substitution.
Chapter 9 Capex cycle: trillion-yuan investment, capacity expansion curve
Memory is the most capital-intensive semiconductor subsegment. A modern DRAM or NAND fab requires USD 10-20 billion per site capex. China's cumulative memory capex 2024-2026 exceeds RMB 800 billion.
YMTC is the core capex sink. From 2016 to end-2025, cumulative investment ~RMB 350 billion across three phases — Phase 1 (RMB 160 billion, 50k wafers/month), Phase 2 (RMB 50 billion, 50k), Phase 3 (registered capital RMB 20.7 billion in September 2025, 50k+, all-domestic). Phase 3's "all-domestic" line has demonstration value far beyond direct capacity contribution.
CXMT cumulative investment exceeds RMB 250 billion. Phase 1 (Hefei EDZ, RMB 150 billion, 240k wafers/month), Phase 2 (RMB 80 billion, 120k). End-2025 total Hefei capacity 300k wafers/month, China's largest DRAM fab. Next capex priorities: D1α node expansion (RMB 20 billion), HBM line construction (RMB 15 billion), Shanghai/other second-tier fab planning (RMB 30 billion).
National IC Industry Investment Fund ("Big Fund") is the primary financier. Phase 1 (2014, RMB 138.7 billion, subscribed RMB 13.558 billion in YMTC, 12.88% stake). Phase 2 (2019, RMB 204.1 billion, subscribed RMB 12.887 billion in YMTC, 12.24%). Phase 3 (May 2024, RMB 344 billion, equal to Phase 1+2 combined). Phase 3 memory investment projected at RMB 100-150 billion — the largest single-fund memory allocation in a decade.
Local-government level: Hefei + Wuhan are the two core cities, plus Beijing, Shenzhen, Shanghai, Nanjing, Chengdu as secondary nodes. Hefei (CXMT + Tongfu + Nexchip) total capex >RMB 500 billion. Wuhan (YMTC + Wuhan Xinxin) total capex >RMB 350 billion.
2024-2027 total chain capex >RMB 1.2 trillion, capacity ramp lifts China's global memory share from ~8% in 2024 to nearly 20% by 2027 — the most profound reshape of memory geography in thirty years.
Equipment order cadence: a DRAM/NAND fab typically places equipment orders 12-18 months before construction completion. YMTC Phase 3 construction completes by mid-2026; corresponding orders to NAURA, AMEC, HwaTsing, KingSemi, CSMI, BoeingSemi, ACM Shanghai have been placed in 2024-2025 — the core driver of domestic equipment makers' 2025-2027 growth.
Chapter 10 Price cycles and demand structure: DRAM, NAND, HBM three curves
Memory is among the most volatile, cyclical semiconductor subsegments. Understanding 2026-2027 requires understanding the past five years.
2020-2022: classic "up-down-up" cycle. H2 2020-H1 2021: work-from-home drove PC/laptop/tablet demand, DRAM up from USD 3 to USD 5 (8Gb), NAND from USD 5 to USD 8 (1Tb). H2 2021-H2 2022: oversupply + demand pullback drove DRAM down to USD 2.5, NAND to USD 3 — "cost-line down" cycle.
2023 was the deepest winter. SK Hynix, Kioxia, Micron all posted losses, Samsung's memory profits halved, all majors cut output 20-30% to stabilize. NAND traded sub-USD 3 most of year, DRAM USD 2-2.5.
2024 was the reversal. AI compute HBM demand + general DRAM cuts drove DRAM up mid-year — 8Gb DDR4 USD 1.8 → 2.5, DDR5 USD 3.5 → 4.5. HBM3 prices rose over 50%. NAND lagged: Samsung + Kioxia cuts held through H2 2024; TLC slowly rose from USD 3.5 to 4.5.
2025 was the "AI-led supercycle". DRAM rose all year — DDR5 8Gb from sub-USD 5 to USD 6.5-7. LPDDR5X similar. HBM3E rose 30%+ mid-year. NAND TLC USD 4.5 → 5.5-6; QLC USD 3.5 → 4.5. Total industry market value jumped from USD 150 billion to USD 180 billion.
2026 forecast: DRAM and HBM continue rising; NAND resumes uptrend after Q2. DDR5 8Gb USD 7-8 year-round; LPDDR5X 9600 Mbps stays high. HBM3E +20% in early 2026; HBM4 ramps in Q2 at ~1.5x HBM3E price. NAND TLC year-end USD 6 → Q2 2026 USD 7; QLC USD 4.5 → 5.5. Cycle remains upward in 2026 but narrower than 2025.
End-market structure: smartphones (~12 billion units; cycle-driven volume but rising per-unit memory speed); AI PC (15% of PC shipments in 2025, 30% in 2026, 50% in 2027 — 32-64 GB DRAM + 1-2 TB SSD); AI servers (200 million units in 2025; per-server 8 GPUs × 192 GB HBM + 8 TB DDR5 + 30-60 TB QLC SSD = USD 50-100K storage per server); smart EVs (15 million units; storage from USD 30-60 per L2-L3 car to USD 200-400 per L4); IoT/TWS (10-15 billion units, USD 0.5-5 per device).
Chapter 11 Policy and ecosystem: Big Fund, 14th Five-Year, Huawei stack effect
Policy is among the most important external variables for China's memory industry over the past decade. From Big Fund Phase 1-3 to 14th Five-Year Plan to Huawei's chip-stack effect to local-government support, a "national-local-industry" policy network has formed.
Big Fund Phase 1: 2014, RMB 138.7 billion; core investments YMTC and Tsinghua Unigroup (>RMB 150 billion).
Big Fund Phase 2: 2019, RMB 204.1 billion; expanded scope to YMTC Phase 2, CXMT, Nexchip, Tongfu advanced packaging (>RMB 200 billion).
Big Fund Phase 3: May 2024, RMB 344 billion. Focus: "advanced manufacturing + equipment + materials + HBM". Memory allocation projected at RMB 100-150 billion; covers YMTC Phase 3, CXMT Phase 2, HBM lines, advanced packaging, electronic chemicals/gases, wafer equipment.
Local government: Hefei + Wuhan as core memory cities. Hefei cumulative fiscal contribution to memory chain over RMB 80 billion in past decade; Wuhan over RMB 60 billion. Beijing + Shenzhen + Shanghai + Nanjing/Chengdu/Xi'an as secondary nodes.
14th Five-Year Plan (2021-2025): designated semiconductors as a "strategic emerging industry" with explicit goal "accelerate memory chip self-reliance". National policies include R&D expense super-deduction (up to 175%), semiconductor enterprise income-tax preferences ("2-free 3-half"), key equipment import exemptions, semiconductor talent personal income tax reductions.
15th Five-Year Plan (2026-2030) direction was established by industry consensus at policy workshops in 2025 — continue supporting memory self-reliance, focus breakthroughs on HBM and advanced DRAM, PLC NAND; lift semiconductor (incl. memory) self-sufficiency from 30-35% in 2025 to 50%+ by 2030.
Huawei's stack effect is the biggest non-governmental pull. Post-sanctions Huawei made "chip self-reliance" a company-level strategy across design/manufacturing/packaging. In storage: Ascend AI chips validated with domestic HBM; Kirin SoCs validated with domestic LPDDR5X; HarmonyOS phones use domestic UFS/SSDs; Huawei Cloud datacenters use YMTC enterprise SSDs at scale.
BYD, Xiaomi, OPPO, vivo, Alibaba, Tencent, ByteDance increasing domestic memory procurement to varying degrees. BYD 2025 automotive NAND/DRAM procurement ~30% domestic; Xiaomi mid-low-end LPDDR5/UFS achieved domestic substitution; AliCloud/TencentCloud/ByteDance enterprise SSD share rising fast.
University and research-institute talent supply: USTC, Tsinghua, Peking University, Fudan, SJTU, HUST, Xidian, SEU. Plus CAS Microelectronics, CAS Shanghai Microsystems, CAS Semiconductors. Together 2000-2500 mid-/high-end semiconductor talents (30-40% memory-related) flow into industry yearly.
Chapter 12 Research-institute judgment: 3-5 year delivery path
Combining the preceding eleven chapters, the research institute offers a systematic judgment for 2026-2030.
DRAM cadence — CXMT mass production of D1z DDR5 in 2026 with year-end 90% yield; D1α (14 nm) R&D complete in H2 2026; D1α commercial production in 2027; D1β (12 nm) in 2028-2029; D1γ (10 nm) in 2030. If achieved, CXMT closes the gap with Samsung/SK/Micron to within 2-3 years by 2030.
NAND cadence — YMTC X5 (300L-equivalent) in 2026; X6 (400L-equivalent) in 2027; 500L+ in 2028-2029; 600L+ in 2030 with PLC. If achieved, YMTC maintains roughly same-generation parity with Samsung/Kioxia/SK Hynix.
HBM cadence — CXMT + Tongfu HBM3 12-Hi in 2026; HBM3E 12-Hi in 2027; HBM4 12-Hi in 2028; HBM4 16-Hi in 2029; HBM5 in 2030. The gap narrows from "two generations behind" in 2026 to "one generation behind" by 2030.
Capacity ramp — YMTC from 130k wafers/month in 2025 to 150k in 2026, 200k in 2027, 250k in 2028. CXMT from 300k in 2025 to 360k in 2026, 420k in 2027, 500k in 2028. Combined capacity rises from 430k to 750k by 2028, lifting global share from 8% to 15%.
HBM market share — China's HBM goes from <1% global in 2026 to 2-3% in 2027, 5-7% in 2028, 10% in 2029, 12-15% in 2030.
Module ecosystem — Longsys + Biwin + DMOST + Shannon combined revenue from RMB 80 billion in 2025 to RMB 100 billion in 2026, RMB 120 billion in 2027, RMB 140 billion in 2028.
Price cycle — DRAM and HBM up 2025-2027; brief 2028 correction possible; NAND up modestly 2025-2026, resumes uptrend with AI-server QLC/PLC SSD pull in 2027-2028.
Localization — equipment localization from 30% in 2025 to 70% in 2030; materials from 35% to 65%; EDA from 15% to 40%; HBM from <1% to 12-15%.
International market — YMTC and CXMT products enter non-US markets in 2026-2028 — Europe, Southeast Asia, India, Middle East, South America. International share rises from <5% in 2025 to 15-20% in 2028.
Overall judgment: China's memory industry will complete the leap from "regional player" to "global third tier" by 2030. DRAM closes to 2-3 years from Samsung/SK/Micron; NAND remains same-generation; HBM gap narrows from two generations to one; module ecosystem reaches RMB 100 billion+; chain localization breaks 60%; international share breaks 15%. This is the research-institute's long-tracking judgment from 「Tianxia Gongchang」(天下工厂) — the source of our confidence in China's semiconductor self-reliance path.
Chapter 13 Risk factors: overseas pressure, control escalation, demand softness
Nine risk types may shape 2026-2030 — overseas giant capacity expansion mid-market pressure (70% probability, hedge: front-load low-cost node ramp); export control escalation (60% probability, hedge: full-stack equipment/materials/EDA substitution); consumer electronics demand softness (50% probability, hedge: shift toward enterprise/automotive/AI server); technical-path engineering uncertainty (40% probability, hedge: deeper R&D with domestic equipment vendors); HBM-on-AI coordination (50% probability, hedge: long-term commit + joint dev with Huawei Ascend, Cambricon, Enflame, Biren, Moore Threads); customer concentration (60% probability, hedge: accelerate international expansion 2026-2028); capital markets volatility (30% probability, hedge: IPO cadence tied to operating fundamentals); talent competition and loss (70% probability, hedge: long-term talent programs); IP/patent litigation (50% probability, hedge: deeper patent investment + cross-licensing).
Scenarios: temperate (50% probability — preceding forecasts realize); optimistic (25% — outperforms forecasts); pessimistic (20% — delays 1-2 years); extreme (5% — major external shocks delay 2-3 years). Weighted expected path is "China memory industry reaches third-largest global cluster, 17-19% share, by 2030".
Chapter 14 Data sources and methodology
Primary sources for this study —
First, public annual and quarterly reports from memory IDMs: Samsung Electronics, SK Hynix, Micron Technology, Kioxia, SanDisk, YMTC (private company public disclosures), CXMT (private), Wuhan Xinxin, Nexchip (STAR-listed). Annual, semi-annual, quarterly, and interim disclosures on capacity, revenue, gross margin, customer mix, product lines, capex.
Second, industry research-house market data: Counterpoint Research, TrendForce, IC Insights, SemiAnalysis, Yole Développement. Quarterly and annual reports tracking global DRAM/NAND/HBM share, prices, shipments, customer structures.
Third, listed module-house earnings: Longsys, Biwin, DMOST, Shannon Semiconductor — 2024-2025 periodic reports on revenue, gross margin, inventory, customers, R&D, plans.
Fourth, domestic equipment and materials supplier disclosures: NAURA, AMEC, HwaTsing, KingSemi, CSMI, BoeingSemi, ACM Shanghai, Empyrean, AnJi Microelectronics, Dinglong, YOKE, Huate Gas — public announcements on memory-IDM-related orders, partnerships, product qualifications.
Fifth, mainstream foreign-language media: Nikkei Asia, Reuters, Bloomberg, CNBC, The Korea Herald, Tom's Hardware, Blocks & Files, Digitimes, SemiWiki, AnandTech — in-depth memory industry reporting 2025-2026 providing cross-verification with Chinese sources.
Sixth, policy documents and industry fund disclosures: State Council, MIIT, NDRC, MOF, MOST, National IC Industry Investment Fund Phase 1/2/3 — central source for policy drivers and capex investment.
Seventh, industry conferences and white papers: IC China (Q4 2025), SEMICON China, AI Hardware Summit, HBM International Workshop — speeches, white papers, expert reports informing process details, capacity planning, technical paths.
Eighth, 「Tianxia Gongchang」(天下工厂) proprietary data. As a B2B platform with 4.8 million active-factory data, the platform tracks the memory supply chain — factory distribution, capacity dynamics, customer relationships, hiring and bidding signals. This study uses platform data on factory identification, supply-chain mapping, geographic distribution. Readers seeking fine-grained customer search by process / scene / geography for the memory supply chain are welcome to use the platform.
Methodologically the study practices "facts first, cross-checked data, restrained judgment": every key number cross-verified with at least two independent sources; predictions explicitly labeled probabilistic; uncertain environments explicitly noted. The fact-cutoff date is 2026-06-23. Readers should combine this study with their own industry observations and latest news for synthesized judgment. The study does not constitute investment advice.
Memory chips have been one of the most cyclical, competitive, technical, and geopolitically charged semiconductor subsegments over the past thirty years. China's path from "broad absence" to "partial breakthrough" to "full pursuit" is among the most profound structural shifts in global semiconductors in the past decade. By 2030, this shift will release deeper implications — not just the rise of China's memory industry, but the rewriting of the global memory map, and the key sample case for the global-local balance in the AI-compute-era semiconductor chain. The research institute will continue tracking and updating in follow-up reports.